שלום, אני צריך את הקובץ d60base
או כל קובץ אחר שיקשר בין הd60 של מוטורולה לאסמבלר..
בבקשה שכל מי שיכול לעזור לי יצור איתי קשר
ICQ 28839401
או דרך הפורום הזה
תודה
*
* Log:
* 1) Define HC12 I/O register locations (68HC12D60).
* 2) Do not. DO NOT & DO NOT REMOVE THE "MOVB #08,$11". !
* 3) Changed last by shacharM.
*
*
*
*
*
*
*
*
*
*
*-----------------------------------------------------------------------------
* EQUATES
*-----------------------------------------------------------------------------
RAMSTRT: EQU $0000 ;start of ram used
REGSTRT: EQU $1000 ;start of free usage for free addresses
PRGSTRT: EQU $2000 ;start of code
REG_VEC: EQU $0600
CHIP_IO EQU $0800 ;D60 requires register move from 0 to
REGBS EQU CHIP_IO
* ;$0800 to provide complete memory banks
*-----------------------------------------------------------------------------
* start of registers
*
PORTA EQU CHIP_IO+0 ;port A = Address lines A8 - A15
PORTB EQU CHIP_IO+1 ;port B = Address lines A0 - A7
DDRA EQU CHIP_IO+2 ;port A direction register
DDRB EQU CHIP_IO+3 ;port A direction register
PORTE EQU CHIP_IO+8 ;port E = mode,IRQandcontrolsignals
DDRE EQU CHIP_IO+9 ;port E direction register
PEAR EQU CHIP_IO+$A ;port E assignments
MODE EQU CHIP_IO+$B ;Mode register
PUCR EQU CHIP_IO+$C ;port pull-up control register
RDRIV EQU CHIP_IO+$D ;port reduced drive control register
INITRM EQU CHIP_IO+$10 ;Ram location register
INITRG EQU CHIP_IO+$11 ;Register location register
INITEE EQU CHIP_IO+$12 ;EEprom location register
MISC EQU CHIP_IO+$13 ;Miscellaneous Mapping control
RTICTL EQU CHIP_IO+$14 ;Real time clock control
RTIFLG EQU CHIP_IO+$15 ;Real time clock flag
COPCTL EQU CHIP_IO+$16 ;Clock operating properly control
COPRST EQU CHIP_IO+$17 ;COP reset register
*-----------------------------------------------------------------------------
* usage of HPRIO: for encoders and PID. do not use for other applications
INTCR: EQU CHIP_IO+$1E *interrupt control register
HPRIO: EQU CHIP_IO+$1F ;high priority reg
BRKCT0: EQU CHIP_IO+$20 ;Break control register
BRKCT1: EQU CHIP_IO+$21 ;Break control register
BRKAH: EQU CHIP_IO+$22 ; Break address register high
BRKAL: EQU CHIP_IO+$23 ; Break address register low
BRKDH: EQU CHIP_IO+$24 ; Break data register high
BRKDL: EQU CHIP_IO+$25 ; Break data register low
*-----------------------------------------------------------------------------
* 2 key wake up ports - G and H. have same interrupt
*
PORTG: EQU CHIP_IO+$28 ;port G
PORTH: EQU CHIP_IO+$29 ;port H = Key port
DDRG: EQU CHIP_IO+$2A ;port G direction register
DDRH: EQU CHIP_IO+$2B ;port H direction register
KWIEG: EQU CHIP_IO+$2C ;Key wake-up port G enable
KWIEH: EQU CHIP_IO+$2D ;Key wake-up port H enable
KWIFG: EQU CHIP_IO+$2E ;Key wake-up port G flags
KWIFH: EQU CHIP_IO+$2F ;Key wake-up port H flags
*-----------------------------------------------------------------------------
* PLL and XCLK registers. do not change these.
*
SYNR: EQU CHIP_IO+$38 ; Synthesizer / multiplier register
REFDV: EQU CHIP_IO+$39 ; Reference divider register
CGTFLG: EQU CHIP_IO+$3A ; RESERVED
PLLFLG: EQU CHIP_IO+$3B ; PLL flags register
PLLCR: EQU CHIP_IO+$3C ; PLL control register
CLKSEL: EQU CHIP_IO+$3D ; Clock select register
SLOW: EQU CHIP_IO+$3E ; Slow mode divider register
*-----------------------------------------------------------------------------
* PORTP & PWM registers.
*
PWCLK: EQU CHIP_IO+$40 ;PWM clock register
PWPOL: EQU CHIP_IO+$41 ;PWM clock select and polarity
PWEN: EQU CHIP_IO+$42 ;PWM enable register
PWPRES: EQU CHIP_IO+$43 ;PWM Prescale register
PWSCAL0: EQU CHIP_IO+$44 ;PWM Scale 0
PWSCNT0: EQU CHIP_IO+$45 ;PWM scale counter 0
PWSCAL1: EQU CHIP_IO+$46 ;PWM scale 1
PWSCNT1: EQU CHIP_IO+$47 ;PWM scale counter 1
PWCNT0: EQU CHIP_IO+$48 ;PWM channel 0 counter
PWCNT1: EQU CHIP_IO+$49 ;PWM channel 1 counter
PWCNT2: EQU CHIP_IO+$4A ;PWM channel 2 counter
PWCNT3: EQU CHIP_IO+$4B ;PWM channel 3 counter
PWPER0: EQU CHIP_IO+$4C ;PWM channel 0 period
PWPER1: EQU CHIP_IO+$4D ;PWM channel 1 period
PWPER2: EQU CHIP_IO+$4E ;PWM channel 2 period
PWPER3: EQU CHIP_IO+$4F ;PWM channel 3 period
PWDTY0: EQU CHIP_IO+$50 ;PWM channel 0 duty cycle
PWDTY1: EQU CHIP_IO+$51 ;PWM channel 1 duty cycle
PWDTY2: EQU CHIP_IO+$52 ;PWM channel 2 duty cycle
PWDTY3: EQU CHIP_IO+$53 ;PWM channel 3 duty cycle
PWCTL: EQU CHIP_IO+$54 ;PWM control register
PWTST: EQU CHIP_IO+$55 ;reserved
PORTPP: EQU CHIP_IO+$56 ;Port P data register
DDRP: EQU CHIP_IO+$57 ;Port P data direction register
*-----------------------------------------------------------------------------
* A2D converter no. 0.
*
ATDCTL0: EQU CHIP_IO+$60 ;ADC control 0 (reserved)
ATDCTL1: EQU CHIP_IO+$61 ;ADC control 1 (reserved)
ATDCTL2: EQU CHIP_IO+$62 ;ADC control 2
ATDCTL3: EQU CHIP_IO+$63 ;ADC control 3
ATDCTL4: EQU CHIP_IO+$64 ;ADC control 4
ATDCTL5: EQU CHIP_IO+$65 ;ADC control 5
ATDSTAT: EQU CHIP_IO+$66 ;ADC status register hi
*ATDSTAT EQU CHIP_IO+$67 ;ADC status register lo
ATDTEST: EQU CHIP_IO+$68 ;ADC test (reserved)
*ATDTEST EQU CHIP_IO+$69 ;
PORTAD: EQU CHIP_IO+$6F ;port ADC = input only
ADR0H: EQU CHIP_IO+$70 ;ADC result 0 register
ADR1H: EQU CHIP_IO+$72 ;ADC result 1 register
ADR2H: EQU CHIP_IO+$74 ;ADC result 2 register
ADR3H: EQU CHIP_IO+$76 ;ADC result 3 register
ADR4H: EQU CHIP_IO+$78 ;ADC result 4 register
ADR5H: EQU CHIP_IO+$7A ;ADC result 5 register
ADR6H: EQU CHIP_IO+$7C ;ADC result 6 register
ADR7H: EQU CHIP_IO+$7E ;ADC result 7 register
*-----------------------------------------------------------------------------
* Timer module: CAPTURE/COMPARE. pt7 is unique - IC(pulse acc.) or OC
*
TIOS: EQU CHIP_IO+$80 ;timer input/output select
CFORC: EQU CHIP_IO+$81 ;timer compare force
OC7M: EQU CHIP_IO+$82 ;timer output compare 7 mask
OC7D: EQU CHIP_IO+$83 ;timer output compare 7 data
TCNT: EQU CHIP_IO+$84 ;timer counter register hi
*TCNT: EQU CHIP_IO+$85 ;timer counter register lo
TSCR: EQU CHIP_IO+$86 ;timer system control register
TQCR: EQU CHIP_IO+$87 ;reserved
TCTL1: EQU CHIP_IO+$88 ;timer control register 1
TCTL2: EQU CHIP_IO+$89 ;timer control register 2
TCTL3: EQU CHIP_IO+$8A ;timer control register 3
TCTL4: EQU CHIP_IO+$8B ;timer control register 4
TMSK1: EQU CHIP_IO+$8C ;timer interrupt mask 1
TMSK2: EQU CHIP_IO+$8D ;timer interrupt mask 2
TFLG1: EQU CHIP_IO+$8E ;timer flags 1
TFLG2: EQU CHIP_IO+$8F ;timer flags 2
TC0: EQU CHIP_IO+$90 ;timer capture/compare register 0
*TC0: EQU CHIP_IO+$91 ;
TC1: EQU CHIP_IO+$92 ;timer capture/compare register 1
*TC1: EQU CHIP_IO+$93 ;
TC2: EQU CHIP_IO+$94 ;timer capture/compare register 2
*TC2: EQU CHIP_IO+$95 ;
TC3: EQU CHIP_IO+$96 ;timer capture/compare register 3
*TC3: EQU CHIP_IO+$97 ;
TC4: EQU CHIP_IO+$98 ;timer capture/compare register 4
*TC4: EQU CHIP_IO+$99 ;
TC5: EQU CHIP_IO+$9A ;timer capture/compare register 5
*TC5: EQU CHIP_IO+$9B ;
TC6: EQU CHIP_IO+$9C ;timer capture/compare register 6
*TC6: EQU CHIP_IO+$9D ;
TC7: EQU CHIP_IO+$9E ;timer capture/compare register 7
*TC7: EQU CHIP_IO+$9F ;
PACTL: EQU CHIP_IO+$A0 ;pulse accumulator controls
PAFLG: EQU CHIP_IO+$A1 ;pulse accumulator flags
PACN3: EQU CHIP_IO+$A2 ;pulse accumulator counter 3
PACN2: EQU CHIP_IO+$A3 ;pulse accumulator counter 2
PULSA: EQU CHIP_IO+$A2 ;pulse accumulator counter b
PULSB: EQU CHIP_IO+$A5 ;pulse accumulator counter a
PACN1: EQU CHIP_IO+$A4 ;pulse accumulator counter 1
PACN0: EQU CHIP_IO+$A5 ;pulse accumulator counter 0
MCCTL: EQU CHIP_IO+$A6 ;Modulus down conunter control
MCFLG: EQU CHIP_IO+$A7 ;down counter flags
ICPACR: EQU CHIP_IO+$A8 ;Input pulse accumulator control
DLYCT: EQU CHIP_IO+$A9 ;Delay count to down counter
ICOVW: EQU CHIP_IO+$AA ;Input control overwrite register
ICSYS: EQU CHIP_IO+$AB ;Input control system control
TIMTST: EQU CHIP_IO+$AD ;timer test register
PORTT: EQU CHIP_IO+$AE ;port T = Timer port
DDRT: EQU CHIP_IO+$AF ;port T direction register
PBCTL: EQU CHIP_IO+$B0 ; Pulse accumulator B control
PBFLG: EQU CHIP_IO+$B1 ; Pulse accumulator B flags
PA3H: EQU CHIP_IO+$B2 ; Pulse Accumulator counter 3
PA2H: EQU CHIP_IO+$B3 ; Pulse Accumulator counter 2
PA1H: EQU CHIP_IO+$B4 ; Pulse Accumulator counter 1
PA0H: EQU CHIP_IO+$B5 ; Pulse Accumulator counter 0
MCCNT: EQU CHIP_IO+$B6 ; Modulus down counter register
*MCCNTL: EQU CHIP_IO+$B7 ; low byte
TCOH: EQU CHIP_IO+$B8 ; Capture 0 holding register
TC1H: EQU CHIP_IO+$BA ; Capture 1 holding register
TC2H: EQU CHIP_IO+$BC ; Capture 2 holding register
TC3H: EQU CHIP_IO+$BE ; Capture 3 holding register
*-----------------------------------------------------------------------------
* SCI 0 serial 0
*
SC0BDH: EQU CHIP_IO+$C0 ;sci 0 baud reg hi byte
SC0BDL: EQU CHIP_IO+$C1 ;sci 0 baud reg lo byte
SC0CR1: EQU CHIP_IO+$C2 ;sci 0 control1 reg
SC0CR2: EQU CHIP_IO+$C3 ;sci 0 control2 reg
SC0SR1: EQU CHIP_IO+$C4 ;sci 0 status reg 1
SC0SR2: EQU CHIP_IO+$C5 ;sci 0 status reg 2
SC0DRH: EQU CHIP_IO+$C6 ;sci 0 data reg hi
SC0DRL: EQU CHIP_IO+$C7 ;sci 0 data reg lo
*-----------------------------------------------------------------------------
* SCI 1 serial 1
*
SC1BDH: EQU CHIP_IO+$C8 ;sci 1 baud reg hi byte
SC1BDL: EQU CHIP_IO+$C9 ;sci 1 baud reg lo byte
SC1CR1: EQU CHIP_IO+$CA ;sci 1 control1 reg
SC1CR2: EQU CHIP_IO+$CB ;sci 1 control2 reg
SC1SR1: EQU CHIP_IO+$CC ;sci 1 status reg 1
SC1SR2: EQU CHIP_IO+$CD ;sci 1 status reg 2
SC1DRH: EQU CHIP_IO+$CE ;sci 1 data reg hi
SC1DRL: EQU CHIP_IO+$CF ;sci 1 data reg lo
*-----------------------------------------------------------------------------
* SPI 0
*
SP0CR1: EQU CHIP_IO+$D0 ;spi 0 control1 reg
SP0CR2: EQU CHIP_IO+$D1 ;spi 0 control2 reg
SP0BR: EQU CHIP_IO+$D2 ;spi 0 baud reg
SP0SR: EQU CHIP_IO+$D3 ;spi 0 status reg hi
SP0DR: EQU CHIP_IO+$D5 ;spi 0 data reg
PORTS: EQU CHIP_IO+$D6 ;port S = Serial port
DDRS: EQU CHIP_IO+$D7 ;port S direction register
PURDS: EQU CHIP_IO+$D9 ;port S pull-ups register
*-----------------------------------------------------------------------------
* EEPROM registers
*
EEMCR: EQU CHIP_IO+$F0 ;EEprom mode control
EEPROT: EQU CHIP_IO+$F1 ;EEprom block protect reg
EETST: EQU CHIP_IO+$F2 ;EEprom test register
EEPROG: EQU CHIP_IO+$F3 ;EEprom program reg
FEE32LCK: EQU CHIP_IO+$F4 ;Flash 32K lock register
FEE32MCR: EQU CHIP_IO+$F5 ;Flash 32K map register
FEE32CTL: EQU CHIP_IO+$F7 ;Flash 32K control register
FEE28LCK: EQU CHIP_IO+$F8 ;Flash 28K lock register
FEE28MCR: EQU CHIP_IO+$F9 ;Flash 28K map register
FEE28CTL: EQU CHIP_IO+$FB ;Flash 28K control register
*-----------------------------------------------------------------------------
* $FC to $FF have no implementation.
*-----------------------------------------------------------------------------
* msCAN Module: notice the lack of BDLC - upgraded to CAN.
*
CMCR0: EQU CHIP_IO+$100 ;
CMCR1: EQU CHIP_IO+$101 ;
CBTR0: EQU CHIP_IO+$102 ;
CBTR1: EQU CHIP_IO+$103 ;
CRFLG: EQU CHIP_IO+$104 ;
CRIER: EQU CHIP_IO+$105 ;
CTFLG: EQU CHIP_IO+$106 ;
CTCR: EQU CHIP_IO+$107 ;
CIDAC: EQU CHIP_IO+$108 ;
CRXERR: EQU CHIP_IO+$10E ;
CTXERR: EQU CHIP_IO+$10F ;
CIDAR0: EQU CHIP_IO+$110 ;
CIDAR1: EQU CHIP_IO+$111 ;
CIDAR2: EQU CHIP_IO+$112 ;
CIDAR3: EQU CHIP_IO+$113 ;
CIDMR0: EQU CHIP_IO+$114 ;
CIDMR1: EQU CHIP_IO+$115 ;
CIDMR2: EQU CHIP_IO+$116 ;
CIDMR3: EQU CHIP_IO+$117 ;
CIDAR4: EQU CHIP_IO+$118 ;
CIDAR5: EQU CHIP_IO+$119 ;
CIDAR6: EQU CHIP_IO+$11A ;
CIDAR7: EQU CHIP_IO+$11B ;
CIDMR4: EQU CHIP_IO+$11C ;
CIDMR5: EQU CHIP_IO+$11D ;
CIDMR6: EQU CHIP_IO+$11E ;
CIDMR7: EQU CHIP_IO+$11F ;
PCTLCAN: EQU CHIP_IO+$13D ;
PORTCAN: EQU CHIP_IO+$13E ;
DDRCAN: EQU CHIP_IO+$13F ;
CRXB0: EQU CHIP_IO+$140 ; CAN RX buffer thru 14F
TRXB0: EQU CHIP_IO+$150 ; CAN TX buffer 0 thru 15F
TRXB1: EQU CHIP_IO+$160 ; CAN TX buffer 1 thru 16F
TRXB2: EQU CHIP_IO+$170 ; CAN TX buffer 2 thru 17F
PCAN: EQU PORTCAN
DDRC: EQU DDRCAN
*-----------------------------------------------------------------------------
* A2D converter no.1
*
ATD1CTL0: EQU CHIP_IO+$1E0 ;ADC1 control 0 (reserved)
ATD1CTL1: EQU CHIP_IO+$1E1 ;ADC1 control 1 (reserved)
ATD1CTL2: EQU CHIP_IO+$1E2 ;ADC1 control 2
ATD1CTL3: EQU CHIP_IO+$1E3 ;ADC1 control 3
ATD1CTL4: EQU CHIP_IO+$1E4 ;ADC1 control 4
ATD1CTL5: EQU CHIP_IO+$1E5 ;ADC1 control 5
ATD1STAT: EQU CHIP_IO+$1E6 ;ADC1 status register hi
*ATD1STAT EQU CHIP_IO+$1E7 ;ADC1 status register lo
ATD1TEST: EQU CHIP_IO+$1E8 ;ADC1 test (reserved)
*ATD1TEST EQU CHIP_IO+$1E9 ;
SCAN_FLG: EQU $80
PORTAD1: EQU CHIP_IO+$1EF ;port ADC1 = input only
ADR10H: EQU CHIP_IO+$1F0 ;ADC1 result 0 register
ADR11H: EQU CHIP_IO+$1F2 ;ADC1 result 1 register
ADR12H: EQU CHIP_IO+$1F4 ;ADC1 result 2 register
ADR13H: EQU CHIP_IO+$1F6 ;ADC1 result 3 register
ADR14H: EQU CHIP_IO+$1F8 ;ADC1 result 4 register
ADR15H: EQU CHIP_IO+$1FA ;ADC1 result 5 register
ADR16H: EQU CHIP_IO+$1FC ;ADC1 result 6 register
ADR17H: EQU CHIP_IO+$1FE ;ADC1 result 7 register
*-----------------------------------------------------------------------------
* Dbug12 Vector Interrupt Source For 68HC12D60;
*
ORG REG_VEC
FDB *
FDB *
CAN_TXD: FDB * ;MSCAN transmit
CAN_RXD: FDB * ;MSCAN receive
MSERRINT: FDB * ;MSCAN err.
PLSBOVFC: FDB * ;Pulse accmultor B OVF
MCNTINT: FDB * ;modulus down counter UNF
KWUGOH: FDB * ;Port H or G wake up
MSCAN1: FDB * ;MSCAN wake up
ADINT: FDB * ;A2D CONVERTER
SCINT1: FDB * ;SCI1
SCINT0: FDB * ;SCI0
SPINT: FDB * ;SPI
PLS_EDG: FDB * ;PULSE ACC IN EDGE
PLS_OVFC: FDB * ;PULSE ACC OVF
TIM_OVF: FDB * ;TIMER OVERFLOW
TCH7: FDB * ;TIMER CH7
TCH6: FDB * ;TIMER CH6
TCH5: FDB * ;TIMER CH5
TCH4: FDB * ;TIMER CH4
TCH3: FDB * ;TIMER CH3
TCH2: FDB * ;TIMER CH2
TCH1: FDB * ;TIMER CH1
TCH0: FDB * ;TIMER CH0
RTINT: FDB * ;Real time int
IRQINT: FDB * ;IRQ
XIRQINT: FDB * ;XIRQ
ILOP_INT: FDB * ;ILLEGAL OP CODE
TRAP_INT: FDB *
SCINT: EQU SCINT0
*-----------------------------------------------------------------------------
ORG RAMSTRT ;start of D60 ram - $0000.
IBUFSIZ: EQU 15 ; input buffer size
EOT: EQU $04 ; end of text/table character
INBUFF RMB IBUFSIZ ; input buffer, defined but not used
ENDBUFF EQU *
COUNT RMB 1 ; characters read, also unused
*-----------------------------------------------------------------------------
*
;this is D60 start
ORG PRGSTRT
; If programming to Flash, uncomment the following line
; org $1000 ; D60
*-----------------------------------------------------------------------------
*
ORG REGSTRT
ldy #REGSTRT
ldd #0
_gnd:
std 2,y+
cpd #PRGSTRT
blo _gnd
NOP
*
; If programming to Flash, uncomment the following line
; LDS #$7FE
; D60 - initialize the stack pointer (don't do this if under monitor)
*
ORG PRGSTRT
; DO NOT REMOVE THE #08,$11 !!!
START:
MOVB #08,$11 ; post-reset location of INITRG
ENDPROG:
; RTS
JSR COP_RESET ; Disable watch-dog timer
JSR TIMER_INI
JSR ONSCI
JSR AD_INIT
JSR PORTP_INI
JSR CONVERT
SWI
;**********************
; End of main loop *
;**********************
; Initialize the SCI0 for 9600 baud
; Since we're using a 16.0 MHz clock and the Baud rate register is calculated:
; BR = MCLK / (16 * Baud_Rate)
; MCLK = crystal / 2
; BR = 8,000,000 / (16 * 9600) which is 153,600
; BR = 52 which is 34 hex
*-----------------------------------------------------------------------------
; The M68HC12D60 powers on with the COP (Computer Operating Properly)
; watchdog system enabled. If you don't reset it occasionally in your software
; it will reset you. This subroutine will reset the COP.
COP_RESET:
MOVB #$00,COPCTL
LDAA #$55 ; get 1st COP reset value
STAA COPRST ; store it
LDAA #$AA ; get 2nd COP reset value
STAA COPRST ; store it
sei
rts
*-----------------------------------------------------------------------------
PORTP_INI
PWM_INI:
MOVB #$FF,DDRP
; MOVB #$00,PWCLK
MOVB #$08,PWCLK
MOVB #$0F,PWPOL
MOVB #$53,PORTPP
MOVB #$FF,PWPER0 ; Period - Full.
MOVB #$D0,PWDTY0 ; Duty - Half.
MOVB #$FF,PWPER1 ; Period - Full.
MOVB #$D0,PWDTY1 ; Duty - Half.
MOVB #$03,PWEN
RTS
ATSOR MOVB #$00,PWEN
MOVB #$F0,PORTPP
RTS
*-----------------------------------------------------------------------------
AD_INIT
MOVB #$80,ATDCTL2
LDAA #AD_WARMUP
DBNE a,*
MOVB #$00,ATDCTL3
MOVB #$61,ATDCTL4
MOVB #$70,ATDCTL5
RTS
*-----------------------------------------------------------------------------
TIMER_INI
MOVB #$80,TSCR
RTS
*-----------------------------------------------------------------------------
ONSCI:
ldaa #$34 ; get baud rate constant
staa SC0BDL ; store low byte
clr SC0BDH ; clear high byte
ldaa #$00 ; configure SCI0 control registers
staa SC0CR1
ldaa #$0C ; enable transmit and receive
staa SC0CR2
RTS
CONVERT:
MOVB #$50,ATDCTL5
BRCLR ATDSTAT,$80,*
LDAA ADR1H
JSR SPILL
BRA CONVERT
*-------------------------------------
SPILL:
STAA $0000
LDAA $0000
RORA
RORA
RORA
RORA
ANDA #$0F
CMPA #$09
BHI ADD1
MORE1
ADDA #$30
STAA $0001
LDAA $0000
ANDA #$0F
CMPA #$09
BHI ADD2
MORE2
ADDA #$30
STAA $0002
LDAA #EOT
STAA $0003
LDX #$0001
JSR OUTSTRG0 ; send it out serial port
JSR OUTCRLF ; output carriage-return
WAITL:
PSHX
PSHB
LDAB #$06
SB00: LDX #$FFFF
SB11: DBNE X,SB11
DBNE B,SB00
PULB
PULX
RTS
ADD1 ADDA #$07
BRA MORE1
ADD2 ADDA #$07
BRA MORE2
ENDLESS BRA ENDLESS
RTS
;-----------------------------------------
;receive data is ready to be read when RDRF bit is set (=1):
; BRCLR SC0SR1 $20 .....
;SC0SR2: 1 BIT $01: RAF=Receiver Active Flag. set- character is being send
; clear- no receive
;character is read from SC0DR (H)
; Output string of ASCII bytes starting at x until end of text ($04).
OUTSTRG:
JSR OUTCRLF ; output carriage-return
OUTSTRG0:
PSHA ; save a
OUTSTRG1:
LDAA 0,X ; read char into a
CMPA #EOT ; is this end of text?
BEQ OUTSTRG3 ; jump if yes
JSR OUTPUT ; output character
INX ; incriment pointer
BRA OUTSTRG1 ; loop
OUTSTRG3:
PULA ; restore a
RTS
; Output a Carriage return and a line feed. Returns a = cr.
OUTCRLF:
LDAA #$0A ; get LF
JSR OUTPUT ; send it
LDAA #$0D ; get CR
JSR OUTPUT ; send it
LDAA #$00
JSR OUTPUT ; output padding
LDAA #$0D
RTS
; Output A to SCI0
OUTPUT:
OUTSCI2:
LDAB SC0SR1 ; read status
BITB #$80 ; test Transmit Data Register Empty bit
BEQ OUTSCI2 ; loop if TDRE=1
ANDA #$7F ; mask parity
STAA SC0DRL ; send character
RTS
PUTOUT:
OTSCI2
LDAB SC0SR1 ; read status
BITB #$80 ; test Transmit Data Register Empty bit
BEQ OTSCI2 ; loop if TDRE=1
ANDA #255
STAA SC0DRL ; send character
RTS
;shacharM
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