* * HC12 i/o register locations (9s12dp256) * This program was made for the MC9S12DP256 chip to flash on the chip * * Changed by: Shachar Mendelowitz 21/7/03 * Any problem or questions, refer to my emails: * - hahamalek@hotmail.com * - mendiskittle@yahoo.com * * * * ************************************************************************************ ProgStrt: EQU $4000 ;Start of Flash RamTop: EQU $4000 ;Top of RAM ResetVec: EQU $EFFE BootVecBase: EQU $EF80 CHIP_IO EQU $0000 ;256 requires register move from 0 to REGBS EQU CHIP_IO EOT: EQU $04 ; end of text/table character PORTA: equ CHIP_IO+0 ;port a = address lines a8 - a15 PORTB: equ CHIP_IO+1 ;port b = address lines a0 - a7 DDRA: equ CHIP_IO+2 ;port a direction register DDRB: equ CHIP_IO+3 ;port a direction register porte: equ CHIP_IO+8 ;port e = mode,irqandcontrolsignals ddre: equ CHIP_IO+9 ;port e direction register pear: equ CHIP_IO+$a ;port e assignments mode: equ CHIP_IO+$b ;mode register pucr: equ CHIP_IO+$c ;port pull-up control register rdriv: equ CHIP_IO+$d ;port reduced drive control register ebictl: equ CHIP_IO+$e ;e stretch control initrm: equ CHIP_IO+$10 ;ram location register initrg: equ CHIP_IO+$11 ;register location register initee: equ CHIP_IO+$12 ;eeprom location register misc: equ CHIP_IO+$13 ;miscellaneous mapping control mtst0: equ CHIP_IO+$14 ; reserved itcr: equ CHIP_IO+$15 ;interrupt test control register itest: equ CHIP_IO+$16 ;interrupt test register mtst1: equ CHIP_IO+$17 ; reserved partidh: equ CHIP_IO+$1a ;part id high partidl: equ CHIP_IO+$1b ;part id low memsiz0: equ CHIP_IO+$1c ;memory size memsiz1: equ CHIP_IO+$1d ;memory size intcr: equ CHIP_IO+$1e ;interrupt control register hprio: equ CHIP_IO+$1f ;high priority reg bkpct0: equ CHIP_IO+$28 ;break control register bkpct1: equ CHIP_IO+$29 ;break control register bkp0x: equ CHIP_IO+$2a ; break 0 index register bkp0h: equ CHIP_IO+$2b ; break 0 pointer high brp0l: equ CHIP_IO+$2c ; break 0 pointer low bkp1x: equ CHIP_IO+$2d ; break 1 index register bkp1h: equ CHIP_IO+$2e ; break 1 pointer high brp1l: equ CHIP_IO+$2f ; break 1 pointer low ppage: equ CHIP_IO+$30 ;program page register portk: equ CHIP_IO+$32 ;port k data ddrk: equ CHIP_IO+$33 ;port k direction SYNR: equ CHIP_IO+$34 ; synthesizer / multiplier register REFDV: equ CHIP_IO+$35 ; reference divider register ctflg: equ CHIP_IO+$36 ; reserved CRGFLG: equ CHIP_IO+$37 ; pll flags register CRGINT: equ CHIP_IO+$38 ; pll interrupt register CLKSEL: equ CHIP_IO+$39 ; clock select register pllctl: equ CHIP_IO+$3a ; pll control register RTICTL: equ CHIP_IO+$3b ;real time interrupt control COPCTL: equ CHIP_IO+$3c ;watchdog control forbyp: equ CHIP_IO+$3d ; ctctl: equ CHIP_IO+$3e ; armcop: equ CHIP_IO+$3f ;cop reset register tios: equ CHIP_IO+$40 ;timer input/output select cforc: equ CHIP_IO+$41 ;timer compare force oc7m: equ CHIP_IO+$42 ;timer output compare 7 mask oc7d: equ CHIP_IO+$43 ;timer output compare 7 data tcnt: equ CHIP_IO+$44 ;timer counter register hi *tcnt: equ CHIP_IO+$45 ;timer counter register lo tscr: equ CHIP_IO+$46 ;timer system control register ttov: equ CHIP_IO+$47 ;reserved tctl1: equ CHIP_IO+$48 ;timer control register 1 tctl2: equ CHIP_IO+$49 ;timer control register 2 tctl3: equ CHIP_IO+$4a ;timer control register 3 tctl4: equ CHIP_IO+$4b ;timer control register 4 tmsk1: equ CHIP_IO+$4c ;timer interrupt mask 1 tmsk2: equ CHIP_IO+$4d ;timer interrupt mask 2 tflg1: equ CHIP_IO+$4e ;timer flags 1 tflg2: equ CHIP_IO+$4f ;timer flags 2 tc0: equ CHIP_IO+$50 ;timer capture/compare register 0 tc1: equ CHIP_IO+$52 ;timer capture/compare register 1 tc2: equ CHIP_IO+$54 ;timer capture/compare register 2 tc3: equ CHIP_IO+$56 ;timer capture/compare register 3 tc4: equ CHIP_IO+$58 ;timer capture/compare register 4 tc5: equ CHIP_IO+$5a ;timer capture/compare register 5 tc6: equ CHIP_IO+$5c ;timer capture/compare register 6 tc7: equ CHIP_IO+$5e ;timer capture/compare register 7 pactl: equ CHIP_IO+$60 ;pulse accumulator controls paflg: equ CHIP_IO+$61 ;pulse accumulator flags pacn3: equ CHIP_IO+$62 ;pulse accumulator counter 3 pacn2: equ CHIP_IO+$63 ;pulse accumulator counter 2 pacn1: equ CHIP_IO+$64 ;pulse accumulator counter 1 pacn0: equ CHIP_IO+$65 ;pulse accumulator counter 0 mcctl: equ CHIP_IO+$66 ;modulus down conunter control mcflg: equ CHIP_IO+$67 ;down counter flags icpar: equ CHIP_IO+$68 ;input pulse accumulator control dlyct: equ CHIP_IO+$69 ;delay count to down counter icovw: equ CHIP_IO+$6a ;input control overwrite register icsys: equ CHIP_IO+$6b ;input control system control timtst: equ CHIP_IO+$6d ;timer test register pbctl: equ CHIP_IO+$70 ; pulse accumulator b control pbflg: equ CHIP_IO+$71 ; pulse accumulator b flags pa3h: equ CHIP_IO+$72 ; pulse accumulator holding register 3 pa2h: equ CHIP_IO+$73 ; pulse accumulator holding register 2 pa1h: equ CHIP_IO+$74 ; pulse accumulator holding register 1 pa0h: equ CHIP_IO+$75 ; pulse accumulator holding register 0 mccnt: equ CHIP_IO+$76 ; modulus down counter register *mccntl: equ CHIP_IO+$77 ; low byte tcoh: equ CHIP_IO+$78 ; capture 0 holding register tc1h: equ CHIP_IO+$7a ; capture 1 holding register tc2h: equ CHIP_IO+$7c ; capture 2 holding register tc3h: equ CHIP_IO+$7e ; capture 3 holding register atd0ctl0: equ CHIP_IO+$80 ;adc control 0 (reserved) atd0ctl1: equ CHIP_IO+$81 ;adc control 1 (reserved) ATD0CTL2: equ CHIP_IO+$82 ;adc control 2 ATD0CTL3: equ CHIP_IO+$83 ;adc control 3 ATD0CTL4: equ CHIP_IO+$84 ;adc control 4 atd0ctl5: equ CHIP_IO+$85 ;adc control 5 atd0stat: equ CHIP_IO+$86 ;adc status register hi *atd0stat equ CHIP_IO+$87 ;adc status register lo atd0test: equ CHIP_IO+$88 ;adc test (reserved) *atd0test equ CHIP_IO+$89 ; atd0dien: equ CHIP_IO+$8d ; portad0: equ CHIP_IO+$8f ;port adc = input only ADR00H: equ CHIP_IO+$90 ;adc result 0 register ADR01H: equ CHIP_IO+$92 ;adc result 1 register ADR02H: equ CHIP_IO+$94 ;adc result 2 register ADR03H: equ CHIP_IO+$96 ;adc result 3 register ADR04H: equ CHIP_IO+$98 ;adc result 4 register ADR05H: equ CHIP_IO+$9a ;adc result 5 register ADR06H: equ CHIP_IO+$9c ;adc result 6 register ADR07H: equ CHIP_IO+$9e ;adc result 7 register PWME: equ CHIP_IO+$a0 ;pwm enable PWMPOL: equ CHIP_IO+$a1 ;pwm polarity PWMCLK: equ CHIP_IO+$a2 ;pwm clock select register PWMPRCLK: equ CHIP_IO+$a3 ;pwm prescale clock select register PWMCAE: equ CHIP_IO+$a4 ;pwm center align select register PWMCTL: equ CHIP_IO+$a5 ;pwm control register PWMTST: equ CHIP_IO+$a6 ;reserved PWMPRSC: equ CHIP_IO+$a7 ;reserved PWMSCLA: equ CHIP_IO+$a8 ;pwm scale a PWMSCLB: equ CHIP_IO+$a9 ;pwm scale b PWMSCNTA: equ CHIP_IO+$aa ;reserved PWMSCNTB: equ CHIP_IO+$ab ;reserved PWMCNT0: equ CHIP_IO+$ac ;pwm channel 0 counter PWMCNT1: equ CHIP_IO+$ad ;pwm channel 1 counter PWMCNT2: equ CHIP_IO+$ae ;pwm channel 2 counter PWMCNT3: equ CHIP_IO+$af ;pwm channel 3 counter PWMCNT4: equ CHIP_IO+$b0 ;pwm channel 4 counter PWMCNT5: equ CHIP_IO+$b1 ;pwm channel 5 counter PWMCNT6: equ CHIP_IO+$b2 ;pwm channel 6 counter PWMCNT7: equ CHIP_IO+$b3 ;pwm channel 7 counter PWMPER0: equ CHIP_IO+$b4 ;pwm channel 0 period PWMPER1: equ CHIP_IO+$b5 ;pwm channel 1 period PWMPER2: equ CHIP_IO+$b6 ;pwm channel 2 period PWMPER3: equ CHIP_IO+$b7 ;pwm channel 3 period PWMPER4: equ CHIP_IO+$b8 ;pwm channel 4 period PWMPER5: equ CHIP_IO+$b9 ;pwm channel 5 period PWMPER6: equ CHIP_IO+$ba ;pwm channel 6 period PWMPER7: equ CHIP_IO+$bb ;pwm channel 7 period PWMDTY0: equ CHIP_IO+$bc ;pwm channel 0 duty cycle PWMDTY1: equ CHIP_IO+$bd ;pwm channel 1 duty cycle PWMDTY2: equ CHIP_IO+$be ;pwm channel 2 duty cycle PWMDTY3: equ CHIP_IO+$bf ;pwm channel 3 duty cycle PWMDTY4: equ CHIP_IO+$c0 ;pwm channel 0 duty cycle PWMDTY5: equ CHIP_IO+$c1 ;pwm channel 1 duty cycle PWMDTY6: equ CHIP_IO+$c2 ;pwm channel 2 duty cycle PWMDTY7: equ CHIP_IO+$c3 ;pwm channel 3 duty cycle PWMSDN: equ CHIP_IO+$c4 ;pwm shutdown register SC0BDH: equ CHIP_IO+$c8 ;sci 0 baud reg hi byte SC0BD1: equ CHIP_IO+$c9 ;sci 0 baud reg lo byte SC0CR1: equ CHIP_IO+$ca ;sci 0 control1 reg SC0CR2: equ CHIP_IO+$cb ;sci 0 control2 reg SC0SR1: equ CHIP_IO+$cc ;sci 0 status reg 1 SC0SR2: equ CHIP_IO+$cd ;sci 0 status reg 2 SC0DRH: equ CHIP_IO+$ce ;sci 0 data reg hi SC0DRl: equ CHIP_IO+$cf ;sci 0 data reg lo SC1BDH: equ CHIP_IO+$d0 ;sci 1 baud reg hi byte SC1BDl: equ CHIP_IO+$d1 ;sci 1 baud reg lo byte SC1CR1: equ CHIP_IO+$d2 ;sci 1 control1 reg SC1CR2: equ CHIP_IO+$d3 ;sci 1 control2 reg SC1SR1: equ CHIP_IO+$d4 ;sci 1 status reg 1 SC1SR2: equ CHIP_IO+$d5 ;sci 1 status reg 2 SC1DRH: equ CHIP_IO+$d6 ;sci 1 data reg hi SC1DRL: equ CHIP_IO+$d7 ;sci 1 data reg lo spi0cr1: equ CHIP_IO+$d8 ;spi 0 control1 reg spi0cr2: equ CHIP_IO+$d9 ;spi 0 control2 reg spi0br: equ CHIP_IO+$da ;spi 0 baud reg spi0sr: equ CHIP_IO+$db ;spi 0 status reg hi sp0dr: equ CHIP_IO+$dd ;spi 0 data reg ibad: equ CHIP_IO+$e0 ;i2c bus address register ibfd: equ CHIP_IO+$e1 ;i2c bus frequency divider ibcr: equ CHIP_IO+$e2 ;i2c bus control register ibsr: equ CHIP_IO+$e3 ;i2c bus status register ibdr: equ CHIP_IO+$e4 ;i2c bus message data register dlcbcr1: equ CHIP_IO+$e8 ;bdlc control regsiter 1 dlcbsvr: equ CHIP_IO+$e9 ;bdlc state vector register dlcbcr2: equ CHIP_IO+$ea ;bdlc control register 2 dlcbdr: equ CHIP_IO+$eb ;bdlc data register dlcbard: equ CHIP_IO+$ec ;bdlc analog delay register dlcbrsr: equ CHIP_IO+$ed ;bdlc rate select register dlcscr: equ CHIP_IO+$ee ;bdlc control register dlcbstat: equ CHIP_IO+$ef ;bdlc status register spi1cr1: equ CHIP_IO+$f0 ;spi 1 control1 reg spi1cr2: equ CHIP_IO+$f1 ;spi 1 control2 reg spi1br: equ CHIP_IO+$f2 ;spi 1 baud reg spi1sr: equ CHIP_IO+$f3 ;spi 1 status reg hi sp1dr: equ CHIP_IO+$f5 ;spi 1 data reg spi2cr1: equ CHIP_IO+$f8 ;spi 2 control1 reg spi2cr2: equ CHIP_IO+$f9 ;spi 2 control2 reg spi2br: equ CHIP_IO+$fa ;spi 2 baud reg spi2sr: equ CHIP_IO+$fb ;spi 2 status reg hi sp2dr: equ CHIP_IO+$fd ;spi 2 data reg fclkdiv: equ CHIP_IO+$100 ;flash clock divider fsec: equ CHIP_IO+$101 ;flash security register fcnfg: equ CHIP_IO+$103 ;flash configuration register fprot: equ CHIP_IO+$104 ;flash protection register fstat: equ CHIP_IO+$105 ;flash status register fcmd: equ CHIP_IO+$106 ;flash command register eclkdiv: equ CHIP_IO+$110 ;eeprom clock divider ecnfg: equ CHIP_IO+$113 ;eeprom configuration register eprot: equ CHIP_IO+$114 ;eeprom protection register estat: equ CHIP_IO+$115 ;eeprom status register ecmd: equ CHIP_IO+$116 ;eeprom command register atd1ctl0: equ CHIP_IO+$120 ;adc1 control 0 (reserved) atd1ctl1: equ CHIP_IO+$121 ;adc1 control 1 (reserved) atd1ctl2: equ CHIP_IO+$122 ;adc1 control 2 atd1ctl3: equ CHIP_IO+$123 ;adc1 control 3 atd1ctl4: equ CHIP_IO+$124 ;adc1 control 4 atd1ctl5: equ CHIP_IO+$125 ;adc1 control 5 atd1stat: equ CHIP_IO+$126 ;adc1 status register hi *atd1stat equ CHIP_IO+$127 ;adc1 status register lo atd1test: equ CHIP_IO+$128 ;adc1 test (reserved) *atd1test equ CHIP_IO+$129 ; atd1dien: equ CHIP_IO+$12d ;adc1 input enable register portad1: equ CHIP_IO+$12f ;port adc1 = input only adr10h: equ CHIP_IO+$130 ;adc1 result 0 register adr11h: equ CHIP_IO+$132 ;adc1 result 1 register adr12h: equ CHIP_IO+$134 ;adc1 result 2 register adr13h: equ CHIP_IO+$136 ;adc1 result 3 register adr14h: equ CHIP_IO+$138 ;adc1 result 4 register adr15h: equ CHIP_IO+$13a ;adc1 result 5 register adr16h: equ CHIP_IO+$13c ;adc1 result 6 register adr17h: equ CHIP_IO+$13e ;adc1 result 7 register can0ctl0: equ CHIP_IO+$140 ;can0 control register 0 can0ctl1: equ CHIP_IO+$141 ;can0 control register 1 can0btr0: equ CHIP_IO+$142 ;can0 bus timing register 0 can0btr1: equ CHIP_IO+$143 ;can0 bus timing register 1 can0rflg: equ CHIP_IO+$144 ;can0 receiver flags can0rier: equ CHIP_IO+$145 ;can0 receiver interrupt enables can0tflg: equ CHIP_IO+$146 ;can0 transmit flags can0tier: equ CHIP_IO+$147 ;can0 transmit interrupt enables can0tarq: equ CHIP_IO+$148 ;can0 transmit message abort control can0taak: equ CHIP_IO+$149 ;can0 transmit message abort status can0tbel: equ CHIP_IO+$14a ;can0 transmit buffer select can0idac: equ CHIP_IO+$14b ;can0 identfier acceptance control can0rerr: equ CHIP_IO+$14e ;can0 receive error counter can0terr: equ CHIP_IO+$14f ;can0 transmit error counter can0ida0: equ CHIP_IO+$150 ;can0 identifier acceptance register 0 can0ida1: equ CHIP_IO+$151 ;can0 identifier acceptance register 1 can0ida2: equ CHIP_IO+$152 ;can0 identifier acceptance register 2 can0ida3: equ CHIP_IO+$153 ;can0 identifier acceptance register 3 can0idm0: equ CHIP_IO+$154 ;can0 identifier mask register 0 can0idm1: equ CHIP_IO+$155 ;can0 identifier mask register 1 can0idm2: equ CHIP_IO+$156 ;can0 identifier mask register 2 can0idm3: equ CHIP_IO+$157 ;can0 identifier mask register 3 can0ida4: equ CHIP_IO+$158 ;can0 identifier acceptance register 4 can0ida5: equ CHIP_IO+$159 ;can0 identifier acceptance register 5 can0ida6: equ CHIP_IO+$15a ;can0 identifier acceptance register 6 can0ida7: equ CHIP_IO+$15b ;can0 identifier acceptance register 7 can0idm4: equ CHIP_IO+$15c ;can0 identifier mask register 4 can0idm5: equ CHIP_IO+$15d ;can0 identifier mask register 5 can0idm6: equ CHIP_IO+$15e ;can0 identifier mask register 6 can0idm7: equ CHIP_IO+$15f ;can0 identifier mask register 7 can0rxfg: equ CHIP_IO+$160 ;can0 rx foreground buffer thru +CHIP_IO+$16f can0txfg: equ CHIP_IO+$170 ;can0 tx foreground buffer thru +CHIP_IO+$17f can1ctl0: equ CHIP_IO+$180 ;can1 control register 0 can1ctl1: equ CHIP_IO+$181 ;can1 control register 1 can1btr0: equ CHIP_IO+$182 ;can1 bus timing register 0 can1btr1: equ CHIP_IO+$183 ;can1 bus timing register 1 can1rflg: equ CHIP_IO+$184 ;can1 receiver flags can1rier: equ CHIP_IO+$185 ;can1 receiver interrupt enables can1tflg: equ CHIP_IO+$186 ;can1 transmit flags can1tier: equ CHIP_IO+$187 ;can1 transmit interrupt enables can1tarq: equ CHIP_IO+$188 ;can1 transmit message abort control can1taak: equ CHIP_IO+$189 ;can1 transmit message abort status can1tbel: equ CHIP_IO+$18a ;can1 transmit buffer select can1idac: equ CHIP_IO+$18b ;can1 identfier acceptance control can1rerr: equ CHIP_IO+$18e ;can1 receive error counter can1terr: equ CHIP_IO+$18f ;can1 transmit error counter can1ida0: equ CHIP_IO+$190 ;can1 identifier acceptance register 0 can1ida1: equ CHIP_IO+$191 ;can1 identifier acceptance register 1 can1ida2: equ CHIP_IO+$192 ;can1 identifier acceptance register 2 can1ida3: equ CHIP_IO+$193 ;can1 identifier acceptance register 3 can1idm0: equ CHIP_IO+$194 ;can1 identifier mask register 0 can1idm1: equ CHIP_IO+$195 ;can1 identifier mask register 1 can1idm2: equ CHIP_IO+$196 ;can1 identifier mask register 2 can1idm3: equ CHIP_IO+$197 ;can1 identifier mask register 3 can1ida4: equ CHIP_IO+$198 ;can1 identifier acceptance register 4 can1ida5: equ CHIP_IO+$199 ;can1 identifier acceptance register 5 can1ida6: equ CHIP_IO+$19a ;can1 identifier acceptance register 6 can1ida7: equ CHIP_IO+$19b ;can1 identifier acceptance register 7 can1idm4: equ CHIP_IO+$19c ;can1 identifier mask register 4 can1idm5: equ CHIP_IO+$19d ;can1 identifier mask register 5 can1idm6: equ CHIP_IO+$19e ;can1 identifier mask register 6 can1idm7: equ CHIP_IO+$19f ;can1 identifier mask register 7 can1rxfg: equ CHIP_IO+$1a0 ;can1 rx foreground buffer thru +CHIP_IO+$1af can1txfg: equ CHIP_IO+$1b0 ;can1 tx foreground buffer thru +CHIP_IO+$1bf can2ctl0: equ CHIP_IO+$1c0 ;can2 control register 0 can2ctl1: equ CHIP_IO+$1c1 ;can2 control register 1 can2btr0: equ CHIP_IO+$1c2 ;can2 bus timing register 0 can2btr1: equ CHIP_IO+$1c3 ;can2 bus timing register 1 can2rflg: equ CHIP_IO+$1c4 ;can2 receiver flags can2rier: equ CHIP_IO+$1c5 ;can2 receiver interrupt enables can2tflg: equ CHIP_IO+$1c6 ;can2 transmit flags can2tier: equ CHIP_IO+$1c7 ;can2 transmit interrupt enables can2tarq: equ CHIP_IO+$1c8 ;can2 transmit message abort control can2taak: equ CHIP_IO+$1c9 ;can2 transmit message abort status can2tbel: equ CHIP_IO+$1ca ;can2 transmit buffer select can2idac: equ CHIP_IO+$1cb ;can2 identfier acceptance control can2rerr: equ CHIP_IO+$1ce ;can2 receive error counter can2terr: equ CHIP_IO+$1cf ;can2 transmit error counter can2ida0: equ CHIP_IO+$1d0 ;can2 identifier acceptance register 0 can2ida1: equ CHIP_IO+$1d1 ;can2 identifier acceptance register 1 can2ida2: equ CHIP_IO+$1d2 ;can2 identifier acceptance register 2 can2ida3: equ CHIP_IO+$1d3 ;can2 identifier acceptance register 3 can2idm0: equ CHIP_IO+$1d4 ;can2 identifier mask register 0 can2idm1: equ CHIP_IO+$1d5 ;can2 identifier mask register 1 can2idm2: equ CHIP_IO+$1d6 ;can2 identifier mask register 2 can2idm3: equ CHIP_IO+$1d7 ;can2 identifier mask register 3 can2ida4: equ CHIP_IO+$1d8 ;can2 identifier acceptance register 4 can2ida5: equ CHIP_IO+$1d9 ;can2 identifier acceptance register 5 can2ida6: equ CHIP_IO+$1da ;can2 identifier acceptance register 6 can2ida7: equ CHIP_IO+$1db ;can2 identifier acceptance register 7 can2idm4: equ CHIP_IO+$1dc ;can2 identifier mask register 4 can2idm5: equ CHIP_IO+$1dd ;can2 identifier mask register 5 can2idm6: equ CHIP_IO+$1de ;can2 identifier mask register 6 can2idm7: equ CHIP_IO+$1df ;can2 identifier mask register 7 can2rxfg: equ CHIP_IO+$1e0 ;can2 rx foreground buffer thru +CHIP_IO+$1ef can2txfg: equ CHIP_IO+$1f0 ;can2 tx foreground buffer thru +CHIP_IO+$1ff can3ctl0: equ CHIP_IO+$200 ;can3 control register 0 can3ctl1: equ CHIP_IO+$201 ;can3 control register 1 can3btr0: equ CHIP_IO+$202 ;can3 bus timing register 0 can3btr1: equ CHIP_IO+$203 ;can3 bus timing register 1 can3rflg: equ CHIP_IO+$204 ;can3 receiver flags can3rier: equ CHIP_IO+$205 ;can3 receiver interrupt enables can3tflg: equ CHIP_IO+$206 ;can3 transmit flags can3tier: equ CHIP_IO+$207 ;can3 transmit interrupt enables can3tarq: equ CHIP_IO+$208 ;can3 transmit message abort control can3taak: equ CHIP_IO+$209 ;can3 transmit message abort status can3tbel: equ CHIP_IO+$20a ;can3 transmit buffer select can3idac: equ CHIP_IO+$20b ;can3 identfier acceptance control can3rerr: equ CHIP_IO+$20e ;can3 receive error counter can3terr: equ CHIP_IO+$20f ;can3 transmit error counter can3ida0: equ CHIP_IO+$210 ;can3 identifier acceptance register 0 can3ida1: equ CHIP_IO+$211 ;can3 identifier acceptance register 1 can3ida2: equ CHIP_IO+$212 ;can3 identifier acceptance register 2 can3ida3: equ CHIP_IO+$213 ;can3 identifier acceptance register 3 can3idm0: equ CHIP_IO+$214 ;can3 identifier mask register 0 can3idm1: equ CHIP_IO+$215 ;can3 identifier mask register 1 can3idm2: equ CHIP_IO+$216 ;can3 identifier mask register 2 can3idm3: equ CHIP_IO+$217 ;can3 identifier mask register 3 can3ida4: equ CHIP_IO+$218 ;can3 identifier acceptance register 4 can3ida5: equ CHIP_IO+$219 ;can3 identifier acceptance register 5 can3ida6: equ CHIP_IO+$21a ;can3 identifier acceptance register 6 can3ida7: equ CHIP_IO+$21b ;can3 identifier acceptance register 7 can3idm4: equ CHIP_IO+$21c ;can3 identifier mask register 4 can3idm5: equ CHIP_IO+$21d ;can3 identifier mask register 5 can3idm6: equ CHIP_IO+$21e ;can3 identifier mask register 6 can3idm7: equ CHIP_IO+$21f ;can3 identifier mask register 7 can3rxfg: equ CHIP_IO+$220 ;can3 rx foreground buffer thru +CHIP_IO+$22f can3txfg: equ CHIP_IO+$230 ;can3 tx foreground buffer thru +CHIP_IO+$23f ptt: equ CHIP_IO+$240 ;portt data register ptit: equ CHIP_IO+$241 ;portt input register ddrt: equ CHIP_IO+$242 ;portt direction register rdrt: equ CHIP_IO+$243 ;portt reduced drive register pert: equ CHIP_IO+$244 ;portt pull device enable ppst: equ CHIP_IO+$245 ;portt pull polarity select pts: equ CHIP_IO+$248 ;ports data register ptis: equ CHIP_IO+$249 ;ports input register ddrs: equ CHIP_IO+$24a ;ports direction register rdrs: equ CHIP_IO+$24b ;ports reduced drive register pers: equ CHIP_IO+$24c ;ports pull device enable ppss: equ CHIP_IO+$24d ;ports pull polarity select woms: equ CHIP_IO+$24e ;ports wired or mode register ptm: equ CHIP_IO+$250 ;portm data register ptim: equ CHIP_IO+$251 ;portm input register ddrm: equ CHIP_IO+$252 ;portm direction register rdrm: equ CHIP_IO+$253 ;portm reduced drive register perm: equ CHIP_IO+$254 ;portm pull device enable ppsm: equ CHIP_IO+$255 ;portm pull polarity select womm: equ CHIP_IO+$256 ;portm wired or mode register modrr: equ CHIP_IO+$257 ;portm module routing register PTP: equ CHIP_IO+$258 ;portp data register PTIP: equ CHIP_IO+$259 ;portp input register DDRP: equ CHIP_IO+$25a ;portp direction register RDRP: equ CHIP_IO+$25b ;portp reduced drive register PERP: equ CHIP_IO+$25c ;portp pull device enable PPSP: equ CHIP_IO+$25d ;portp pull polarity select PIEP: equ CHIP_IO+$25e ;portp interrupt enable register PIFP: equ CHIP_IO+$25f ;portp interrupt flag register PTH: equ CHIP_IO+$260 ;porth data register ptih: equ CHIP_IO+$261 ;porth input register ddrh: equ CHIP_IO+$262 ;porth direction register rdrh: equ CHIP_IO+$263 ;porth reduced drive register perh: equ CHIP_IO+$264 ;porth pull device enable ppsh: equ CHIP_IO+$265 ;porth pull polarity select pieh: equ CHIP_IO+$266 ;porth interrupt enable register pifh: equ CHIP_IO+$267 ;porth interrupt flag register ptj: equ CHIP_IO+$268 ;portp data register ptij: equ CHIP_IO+$269 ;portp input register ddrj: equ CHIP_IO+$26a ;portp direction register rdrj: equ CHIP_IO+$26b ;portp reduced drive register perj: equ CHIP_IO+$26c ;portp pull device enable ppsj: equ CHIP_IO+$26d ;portp pull polarity select piej: equ CHIP_IO+$26e ;portp interrupt enable register pifj: equ CHIP_IO+$26f ;portp interrupt flag register can4ctl0: equ CHIP_IO+$280 ;can4 control register 0 can4ctl1: equ CHIP_IO+$281 ;can4 control register 1 can4btr0: equ CHIP_IO+$282 ;can4 bus timing register 0 can4btr1: equ CHIP_IO+$283 ;can4 bus timing register 1 can4rflg: equ CHIP_IO+$284 ;can4 receiver flags can4rier: equ CHIP_IO+$285 ;can4 receiver interrupt enables can4tflg: equ CHIP_IO+$286 ;can4 transmit flags can4tier: equ CHIP_IO+$287 ;can4 transmit interrupt enables can4tarq: equ CHIP_IO+$288 ;can4 transmit message abort control can4taak: equ CHIP_IO+$289 ;can4 transmit message abort status can4tbel: equ CHIP_IO+$28a ;can4 transmit buffer select can4idac: equ CHIP_IO+$28b ;can4 identfier acceptance control can4rerr: equ CHIP_IO+$28e ;can4 receive error counter can4terr: equ CHIP_IO+$28f ;can4 transmit error counter can4ida0: equ CHIP_IO+$290 ;can4 identifier acceptance register 0 can4ida1: equ CHIP_IO+$291 ;can4 identifier acceptance register 1 can4ida2: equ CHIP_IO+$292 ;can4 identifier acceptance register 2 can4ida3: equ CHIP_IO+$293 ;can4 identifier acceptance register 3 can4idm0: equ CHIP_IO+$294 ;can4 identifier mask register 0 can4idm1: equ CHIP_IO+$295 ;can4 identifier mask register 1 can4idm2: equ CHIP_IO+$296 ;can4 identifier mask register 2 can4idm3: equ CHIP_IO+$297 ;can4 identifier mask register 3 can4ida4: equ CHIP_IO+$298 ;can4 identifier acceptance register 4 can4ida5: equ CHIP_IO+$299 ;can4 identifier acceptance register 5 can4ida6: equ CHIP_IO+$29a ;can4 identifier acceptance register 6 can4ida7: equ CHIP_IO+$29b ;can4 identifier acceptance register 7 can4idm4: equ CHIP_IO+$29c ;can4 identifier mask register 4 can4idm5: equ CHIP_IO+$29d ;can4 identifier mask register 5 can4idm6: equ CHIP_IO+$29e ;can4 identifier mask register 6 can4idm7: equ CHIP_IO+$29f ;can4 identifier mask register 7 can4rxfg: equ CHIP_IO+$2a0 ;can4 rx foreground buffer thru +CHIP_IO+$2af can4txfg: equ CHIP_IO+$2b0 ;can4 tx foreground buffer thru +CHIP_IO+$2bf ;************************************************************************************************************* ; end registers. ;************************************************************************************************************* ; Boot Loader Pesudo Vectors: ; These are needed ; ORG BootVecBase FDB * ;Reserved FDB * ;Reserved FDB * ;Reserved FDB * ;Reserved FDB * ;Reserved FDB * ;Reserved PWM_Shutdown: FDB * ;Pwm Emergeny shut down PP_Interrupt: FDB * ;Port P interrupt CAN4T: FDB * CAN4R: FDB * CAN4err: FDB * CAN4wakeup: FDB * CAN3T: FDB * CAN3R: FDB * CAN3err: FDB * CAN3wakeup: FDB * CAN2T: FDB * CAN2R: FDB * CAN2err: FDB * CAN2wakeup: FDB * CAN1T: FDB * CAN1R: FDB * CAN1err: FDB * CAN1wakeup: FDB * CAN0T: FDB * CAN0R: FDB * CAN0err: FDB * CAN0wakeup: FDB * FLASH: FDB * EEPROM: FDB * SPI2: FDB * ;Spi2 interrupt SPI1: FDB * ;Spi1 interrupt IIC: FDB * ;Inter IC BDLC: FDB * ;Byte Data Link Communication CRGself: FDB * ;CRG self lock mode CRGlock: FDB * ;CRG PLL lock PACB_OVF: FDB * ;Pulse Acc. B Overflow Modulusdown: FDB * ;Modulus Count Down PHwakeup: FDB * ;Port H wake up PJwakeup: FDB * ;Port J wake up ATD1call: FDB * ;ATD 1 end ATD2call: FDB * ;ATD 2 end SCI1: FDB * ;Sci1 interrupt SCI0: FDB * ;Sci0 interrupt SPI0: FDB * ;Spi0 interrupt PACA_edge: FDB * ;Pulsa ACC. A trigger PAVA_OVF: FDB * ;Pulsa ACC. A Overflow ECT_OVF: FDB * ;TCNT counter Overflow ECT7: FDB * ;ECT0 trigger ECT6: FDB * ;ECT1 trigger ECT5: FDB * ;ECT2 trigger ECT4: FDB * ;ECT3 trigger ECT3: FDB * ;ECT4 trigger ECT2: FDB * ;ECT5 trigger ECT1: FDB * ;ECT6 trigger ECT0: FDB * ;ECT7 trigger RTinterrupt: FDB * ;Real Time Interrupt= RTI IRQ_edge: FDB * ;IRQ XIEQ_edge: FDB * ;XIRQ SWinterrupt: FDB * ;SoftWare Interrupt UniTrap: FDB * ;Unimplemented Trap COPresetfail: FDB * COPmonfail: FDB * RESET: FDB * ;************************************************************************************************************* ; added equates. AD_WARMUP: equ $C8 ;needed for the ATD delay at startup ; end of added equates ;************************************************************************************************************* ; Start of the universe. ; It is possible to include the previous. ; Never the less it is recomended to continue to the ProgramStart ; and by the end of the inits , do a JMP in another file ; and in your file do: ; #include c:\hc12\reg912.asm ; or where ever the file is (full path is recomended) ; ; ; ; ; - Shachar ; org ProgStrt ;start here! start here! flashit! lds #RamTop ;we'd want to stack it right? ProgramStart: JSR COP_RESET ldd #52 ;still in 8 mhz mode JSR SetSerial JSR PllClkSelect JSR SetSerial JSR ATD JSR SetPp ; JMP ;enter your address BRA * ;*----------------------------------------------------------------------------- ; The MC9S12DP256 powers on with the COP (Computer Operating Properly) ; watchdog system enabled. If you don't reset it occasionally in your software ; it will reset you. This subroutine will reset the COP. COP_RESET: MOVB #$55,COPCTL ;Durn cops. MOVB #$AA,COPCTL sei ;dont interrupt! rts ;*------------------------------------------------------------------------------ ; Set processor clock to 24MHz ; PLLCLK = 2 x 8Mhz * (SYNR+1)/(REFDV+1) ; Wait until PLL is in lock ; ; PllClkSelect: ldab #1 stab REFDV ldab #2 stab SYNR ;2*8mhz*(2+1)/(1+1) brclr CRGFLG,$08,* ;go sychornically into BUS ldab #128 ;0x80 stab CLKSEL ;PllSelect=1 - work by PLL Clock , not by OSclock rts ;*------------------------------------------------------------------------------ ; Set baudrate to 9600 ; choose in D: 52 for 8 mhz ; 156 for 24 mhz ; Put the wanted value in D before : LDD #WantedValue ; JSR SetSerial ; if no D is selected, then 156 is selected under 24 mhz ; ; SetSerial: ;Under 8 mhz cpd #52 beq setit cpd #156 beq setit ldd #156 setit: std SC0BDH ;SCI0BD = 52 --> SCI baud rate (52 at 8 Mhz, 156 at 24 Mhz) ldab #12 stab SC0CR2 ;SCI0CR2 = 0x0C -->enable transmitter and receiver SetSerialOut: rts ;------------------------------------------------------------------------------- ; ATD intializations ; ATD: ldab #$80 stab ATD0CTL2 ;normal atd function (converter 0) stab ATD1CTL2 LDAA #AD_WARMUP DBNE a,* ldab #0 stab ATD0CTL3 ;convert all 8 channels stab ATD1CTL3 ;convert all 8 channels ldab #$E1 stab ATD0CTL4 ;8 bit mode, 2 atd clocks, /8 prescale stab ATD1CTL4 ldab #$30 stab ATD0CTL5 stab ATD1CTL5 rts ;------------------------------------------------------------------------------- ; Port P intializations ; SetPp: BSET PWME,#$FF ;enable all pwm chanels. MSB - which is PWM7 - will turn on the RED LED BSET PWMPOL,#$FF ;polarity choice BCLR PWMCLK,#$FF ;PWMCLKi = 0 or 1 , chooses between clock A (or B) and clock SA (or SB) BSET PWMPRCLK,#$11 ;A & B clocks prescalers select = %00010001 MOVB #$FF,PWMPER0 ;We got 8 PWM channels. MOVB #$FF,PWMPER1 ;Putting an $FF divider will divide 5 volts at maximum resolution MOVB #$FF,PWMPER2 ;concentration of 2 channels (pwm 16 bit mode) will become a divider MOVB #$FF,PWMPER3 ;of $FFFF - very high resolution. MOVB #$FF,PWMPER4 MOVB #$FF,PWMPER5 MOVB #$FF,PWMPER6 MOVB #$FF,PWMPER7 ;now you can enable the PWMDTYx {x=0,1,..,7) as long as: 0 < PWMDTYx < PWMPERx MOVB #$40,PWMDTY0 RTS ;*********************************************************************************************************************** ; ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ; Utility Routines *** *** *** *** *** *** *** *** *** *** *** *** *** *** ;----------------------------------------------------------------------------------------------------------------------- ; ; ; ;------------------------ ;Prints A on the screen ; ; PRINTA: STAA $1000 LDAA $1000 RORA RORA RORA RORA ANDA #$0F CMPA #$09 BHI ADD1 MORE1 ADDA #$30 STAA $1001 LDAA $1000 ANDA #$0F CMPA #$09 BHI ADD2 MORE2 ADDA #$30 STAA $1002 LDAA #EOT STAA $1003 LDX #$1001 JSR OUTSTRG0 ; send it out serial port WAITL: PSHX PSHB LDAB #$06 SB00: LDX #$FFFF SB11: DBNE X,SB11 DBNE B,SB00 PULB PULX RTS ADD1 ADDA #$07 BRA MORE1 ADD2 ADDA #$07 BRA MORE2 ENDLESS BRA ENDLESS RTS ;----------------------------------------- ;receive data is ready to be read when RDRF bit is set (=1): ; BRCLR SC0SR1 $20 ..... ;SC0SR2: 1 BIT $01: RAF=Receiver Active Flag. set- character is being send ; clear- no receive ;character is read from SC0DR (H) ; Output string of ASCII bytes starting at x until end of text ($04). OUTSTRG: JSR OUTCRLF ; output carriage-return OUTSTRG0: PSHA ; save a OUTSTRG1: LDAA 0,X ; read char into a CMPA #EOT ; is this end of text? BEQ OUTSTRG3 ; jump if yes JSR OUTPUT ; output character INX ; incriment pointer BRA OUTSTRG1 ; loop OUTSTRG3: PULA ; restore a RTS ; Output a Carriage return and a line feed. Returns a = cr. ENTER: OUTCRLF: LDAA #$0A ; get LF JSR OUTPUT ; send it LDAA #$0D ; get CR JSR OUTPUT ; send it LDAA #$00 JSR OUTPUT ; output padding LDAA #$0D RTS ; Output A to SCI0 OUTPUT: OUTSCI2: LDAB SC0SR1 ; read status BITB #$80 ; test Transmit Data Register Empty bit BEQ OUTSCI2 ; loop if TDRE=1 ANDA #$7F ; mask parity STAA SC0DRL ; send character RTS ;end of PRINTF ;--------------------------------------------------------------------------------------------------------------------- ;*********************************************************************************************************************** ; ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ; Intterupt enable routines *** *** *** *** *** *** *** *** *** *** *** *** *** ;----------------------------------------------------------------------------------------------------------------------- ; ; Change paramaters inside if needed ; Change name of intterupts if needed (in BootLoader Table) ; 1) RTenable: RTI setup ; 2) SCI: serial setup ; 3) ECT: port T setip ; ; ; ; ; ; ; ; ; ;----------------------------------- RTenable: sei bset CRGINT,#$80 bset RTICTL,#%00010000 rts ;----------------------------------- SCIenable: rts ;----------------------------------- PTenable: rts ;----------------------------------- ;*********************************************************************************************************************** ; ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ; Acctual Interrupt Routnines *** *** *** *** *** *** *** *** *** *** *** *** *** ;----------------------------------------------------------------------------------------------------------------------- ; 1) Swi routine ; ; ; ; ; ; ; This routine, when an SWI occures on program, displays D,X and Y SWIroutine: PSHY PSHX PSHD PSHD JSR ENTER ;------------------------- LDAA #'D' JSR OUTPUT LDAA #'=' JSR OUTPUT ;------------------------- PULD JSR PRINTA PULD TFR b,a JSR PRINTA JSR ENTER ;------------------------- LDAA #'X' JSR OUTPUT LDAA #'=' JSR OUTPUT ;------------------------- PULX XGDX PSHD JSR PRINTA PULD TFR b,a JSR PRINTA JSR ENTER ;------------------------- LDAA #'Y' JSR OUTPUT LDAA #'=' JSR OUTPUT ;------------------------- PULX XGDX PSHD JSR PRINTA PULD TFR b,a JSR PRINTA JSR ENTER ;------------------------- BRA * RTI ;*********************************************************************************************************************** ; ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ; BootLoad Vectors Table *** *** *** *** *** *** *** *** *** *** *** *** *** *** ;----------------------------------------------------------------------------------------------------------------------- ;Erase this and Nothing will work. ;BootLoader Pesudo-Vector Table ; ORG ResetVec fdb ProgStrt ;RESET - where execution begins after a hard reset to bootpesuado vecotr ORG SWinterrupt fdb SWIroutine ;-------------------------------------------------------------------------------------------------------- ;Shachar M